/*
 * Arm SCP/MCP Software
 * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#ifndef SCP_MMAP_H
#define SCP_MMAP_H

/* SCP ROM and RAM base addresses */
#define SCP_BOOT_ROM_BASE 0x00000000
#define SCP_RAM_BASE      0x10000000

/* SCP ROM and RAM firmware size loaded on main memory */
#define SCP_BOOT_ROM_SIZE (512 * 1024)
#define SCP_RAM_SIZE      (512 * 1024)

/* SCP trusted and non-trusted RAM base address */
#define SCP_TRUSTED_RAM_BASE    (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x04000000)
#define SCP_NONTRUSTED_RAM_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x06000000)

/* Secure Shared memory between AP and SCP */
#define SCP_AP_SHARED_SECURE_BASE (SCP_TRUSTED_RAM_BASE)
#define SCP_AP_SHARED_SECURE_SIZE (4 * FWK_KIB)

/* Non-secure Shared memory between AP and SCP */
#define SCP_AP_SHARED_NONSECURE_BASE (SCP_NONTRUSTED_RAM_BASE)
#define SCP_AP_SHARED_NONSECURE_SIZE (4 * FWK_KIB)

#define SCP_SOC_EXPANSION3_BASE                UINT32_C(0x40000000)
#define SCP_PERIPHERAL_BASE                    UINT32_C(0x44000000)
#define SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE UINT32_C(0x50000000)
#define SCP_SYSTEM_ACCESS_PORT0_BASE           UINT32_C(0x60000000)
#define SCP_SYSTEM_ACCESS_PORT1_BASE           UINT32_C(0xA0000000)

#define SCP_CMN_BOOKER_BASE (SCP_SYSTEM_ACCESS_PORT0_BASE + 0x10000000)
#define SCP_UART_BOARD_BASE (SCP_SYSTEM_ACCESS_PORT0_BASE + 0x3FF70000)
#define SCP_PIK_SCP_BASE    (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE)

#define SCP_REFCLK_CNTCONTROL_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x2A430000)
#define SCP_REFCLK_CNTCTL_BASE     (SCP_PERIPHERAL_BASE + 0x0000)
#define SCP_REFCLK_CNTBASE0_BASE   (SCP_PERIPHERAL_BASE + 0x1000)

#define SCP_PIK_CLUSTER_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0x60000)
#define SCP_PIK_SYSTEM_BASE  (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0x40000)
#define SCP_PIK_DPU_BASE     (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0xE0000)

#define SCP_UTILITY_BUS_BASE \
    (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0x1000000)
#define SCP_PPU_CLUSTER_BASE (SCP_UTILITY_BUS_BASE + 0x30000)
#define SCP_PPU_CORE_BASE(n) (SCP_UTILITY_BUS_BASE + 0x80000 + (n * 0x100000))

#define SCP_PPU_SYS0_BASE (SCP_PIK_SYSTEM_BASE + 0x1000)

#define SCP_MHU_AP_BASE (SCP_PERIPHERAL_BASE)

#define SCP_MHU_SCP_AP_RCV_NS_CLUS0 (SCP_MHU_AP_BASE + 0x2000)
#define SCP_MHU_SCP_AP_SND_NS_CLUS0 (SCP_MHU_AP_BASE + 0x3000)
#define SCP_MHU_SCP_AP_RCV_S_CLUS0  (SCP_MHU_AP_BASE + 0x4000)
#define SCP_MHU_SCP_AP_SND_S_CLUS0  (SCP_MHU_AP_BASE + 0x5000)

#define SCP_PLL_BASE         (SCP_SOC_EXPANSION3_BASE + 0x03000000)
#define SCP_PLL_SYSPLL       (SCP_PLL_BASE + 0x00000000)
#define SCP_PLL_DISPLAY      (SCP_PLL_BASE + 0x00000014)
#define SCP_PLL_PIX0         (SCP_PLL_BASE + 0x00000018)
#define SCP_PLL_PIX1         (SCP_PLL_BASE + 0x0000001C)
#define SCP_PLL_INTERCONNECT (SCP_PLL_BASE + 0x00000020)

#define SCP_PLL_CPU0 (SCP_PLL_BASE + 0x00000100)
#define SCP_PLL_CPU1 (SCP_PLL_BASE + 0x00000104)
#define SCP_PLL_CPU2 (SCP_PLL_BASE + 0x00000108)

/* AP Context Area */
#define SCP_AP_CONTEXT_BASE \
    (SCP_AP_SHARED_SECURE_BASE + SCP_AP_SHARED_SECURE_SIZE - \
     SCP_AP_CONTEXT_SIZE)
#define SCP_AP_CONTEXT_SIZE (64)

/* SDS Memory Region */
#define SCP_SDS_MEM_BASE (SCP_AP_SHARED_SECURE_BASE)
#define SCP_SDS_MEM_SIZE (3520)

/* SCMI Secure Payload Areas */
#define SCP_SCMI_PAYLOAD_SIZE       (128)
#define SCP_SCMI_PAYLOAD_S_A2P_BASE (SCP_SDS_MEM_BASE + SCP_SDS_MEM_SIZE)
#define SCP_SCMI_PAYLOAD_S_P2A_BASE \
    (SCP_SCMI_PAYLOAD_S_A2P_BASE + SCP_SCMI_PAYLOAD_SIZE)

/* SCMI Non-Secure Payload Areas */

#define SCP_SCMI_PAYLOAD0_NS_A2P_BASE (SCP_AP_SHARED_NONSECURE_BASE)
#define SCP_SCMI_PAYLOAD0_NS_P2A_BASE \
    (SCP_SCMI_PAYLOAD0_NS_A2P_BASE + SCP_SCMI_PAYLOAD_SIZE)
#define SCP_SCMI_PAYLOAD1_NS_A2P_BASE \
    (SCP_SCMI_PAYLOAD0_NS_P2A_BASE + SCP_SCMI_PAYLOAD_SIZE)
#define SCP_SCMI_PAYLOAD1_NS_P2A_BASE \
    (SCP_SCMI_PAYLOAD1_NS_A2P_BASE + SCP_SCMI_PAYLOAD_SIZE)

#endif /* SCP_MMAP_H */
